FIG. 10 to FIG. 14 correspond to FIG. 1 to FIG. 5 of U.S. Patent Publication No. 2009/0097299, respectively.
As shown in FIG. 10, a semiconductor memory device 10 according to U.S. 2009/0097299 includes a stacked layer of a ferroelectric layer 13 and a semiconductor layer 14. In the semiconductor memory device 10, a first electrode 12 is formed on the stacking layer at the ferroelectric layer 13 side and a plurality of second electrodes 15a, 15b and 15c are formed on the stacked layer at the semiconductor layer 14 side. These layers are formed on a substrate 11.
FIGS. 11A and 11B show an initial state of the semiconductor memory device of FIG. 10. FIG. 11A is a cross-sectional perspective view and FIG. 11B is an equivalent circuit diagram.
For example, when an n-type semiconductor material is used for the semiconductor layer 14, all directions of polarization 16 are oriented in the same direction so that the polarization 16 of the ferroelectric layer 13 is coupled with electrons (i.e., majority carriers) of the semiconductor layer 14 in an initial state. In this case, two-dimensional electrons 17 are induced by the polarization of the ferroelectric layer 13 and are accumulated around the interface between the semiconductor layer 14 and the ferroelectric layer 13. In this state, the semiconductor layer 14 is in a low resistance state. Thus, the semiconductor layer 14 serves as a channel in which a current flows in the same manner as a metal electrode and can be used as the same kind of electrodes as a metal electrode. In such a case, as shown in FIG. 11B, a conduction state between the semiconductor layer 14 and each of the second electrodes 15a, 15b and 15c is short-circuited.
In this state, as shown in FIG. 12A, when a bias voltage relative to the first electrode 12 is applied to the second electrode 15c, only the polarization in a part of the ferroelectric layer 13 located in which the second electrode 15c is formed is inverted, and the polarization is oriented in the direction which causes exclusion of electrons in the semiconductor layer 14. Accordingly, only the part 18 of the semiconductor layer 14 located in the region in which the second electrode 15c is formed is depleted and thus becomes in a high resistance state. As a result, as shown in FIG. 12B, a state between the semiconductor layer 14 and the second electrode 15c is an open-circuited state.
FIGS. 13A, 13B and 13C show two resistance states of the part of the semiconductor layer 14 located in a region in which the second electrode 15 is formed. FIG. 13A is a cross-sectional view of the part when it is in a low resistance state, FIG. 13B is a cross-sectional view of the part when it is in a high resistance state, and FIG. 13C is a table showing sheet resistance values between the semiconductor layer 14 and the second electrode 15. As shown in the table, each of the parts of the semiconductor layer 14 located in regions in which the second electrodes 15a, 15b and 15c are formed can be in either of two states having different sheet resistance values because of the polarization assist effect of the ferroelectric layer 13.
In the state shown in FIG. 13B, when a low bias voltage relative to the first electrode 12 is applied to the second electrode 15, the polarization of the ferroelectric layer 13 is inverted again. Thus, the polarization is oriented in the direction in which electrons are accumulated and the part 18 of the semiconductor layer 14 located in the region in which the second electrode 15 is formed is back to a low resistance state. As a result, the conduction state between the semiconductor layer 14 and the second electrode 15 becomes in a short circuit state again.
FIGS. 14A, 14B and 14C show measurements for resistance values of the semiconductor layer 14 using a four-probe method. FIG. 14A is a diagram illustrating how the resistance value of the semiconductor layer 14 is measured when it is in a low resistance state where two-dimensional electrons are accumulated, FIG. 14B is a diagram illustrating how the resistance value of the semiconductor layer 14 is measured when it is in a high resistance state where two-dimensional electrons are excluded, and FIG. 14C is a table showing respective measurement results. As shown in the table of FIG. 14C, the resistance value of the semiconductor layer 14 is about 1×103 ohm per square or less in the low resistance state and about 1×106 ohm per square or more in the high resistance state.